Nanostructures on Semiconductor Surfaces

Moore's Law (named after George Moore, head of Intel) states that the density of transistors on a silicon chip will double every three years. This empirical observation has become encoded into the Semiconductor Industry Association's Roadmap, an extraordinary document which plots out the development of semiconductor technological development over the course of thirty years, regardless of the availability of the requisite processing abilities.

However, this relentless drive for increased density relies on the ability to continue miniaturizing the transistors. And there are several fundamental physical limits on the sizes of transistors, beyond which quantum mechanics may start to play a role: the thickness of the oxide layer under a CMOS transistor gate (already only a few nanometres); and the size of the gate of the transistor (once it drops below ~100nm, there could be leakage across it due to tunnelling of electrons); as well as these, there are physical limits on the lithography processes used to build these devices.

Since these physical limits are being approached, many manufacturers are looking for alternative solutions. One of these is to use the quantum mechanical effects which may plague conventional transistors; this will allow the shrinking of devices to sizes of only a few nanometres. The idea is to use arrays of quantum dots (small islands which confine electrons, and separate their energy levels by more than the random thermal energy of one electron) to replace conventional CMOS transistors.

It so happens that if one semiconductor is grown on another under strain (e.g. Ge on Si or InAs on GaAs), the strain results in the spontaneous formation of small islands which are about the right size to act as quantum dots near room temperature. This only happens on one face of these semiconductors (the (001) face); understanding why this happens, and also how the growth of these islands proceeds, will give valuable information for controlling their growth, and eventually creating nanostructure-based computers.

Using the Conquest code, and in close collaboration with a number of experimental groups, we are investigating the effects of strain during the growth of Ge on Si, and InAs on GaAs. As Conquest allows us to perform ab initio calculations on several tens of thousands of atoms, we will be able eventually to model the structure of a small semiconductor cluster on a (001) surface.

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Last updated 20 December 2000